Implementation of Clock Gating for Power Optimizing in Synchronous Design
نویسندگان
چکیده
منابع مشابه
Clock Gating for Dynamic Power Reduction in Synchronous Circuits
In this paper clock gating technique is presented for low power VLSI (very large scale integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous circuits. Clock-gating is a well-known technique to reduce clock power. In clock gating clock to an idle block is disabled. Thus sign...
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A new technique of clock gating is presented to reduce dynamic power consumption. This new clock gating technique is applied on a synchronous design. Here the synchronous design is FIFO (First -in -Firstout). With the help of clock gating method unwanted switching activities can be reduced. Mainly Tri-state Buffer is used to design this new low power approach. The RTL schematic of FIFO without ...
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This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer ...
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Power reduction in dynamic circuits became an important factor today. In this thesis, we designs an ALU using the popular power reduction techniques named clock gating and precomputation based sequential logic optimization for low power . It reduces the power consumption by reducing the dynamic switching power. Power reduction deals with synthesis, design at circuit level and placement and rout...
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Along with the progress of VLSI technology delay buffers plays an increasingly critical role on affecting the circuit design and performance. This paper presents the design of a low power buffer. A gated clock ring counter is used to access the memory. The ring counter uses Double edge triggered flip flops instead of traditional flip flops to half the operating frequency. Also combinational ele...
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ژورنال
عنوان ژورنال: Tikrit Journal of Engineering Sciences
سال: 2018
ISSN: 1813-162X,2312-7589
DOI: 10.25130/tjes.25.3.03